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Metra Cecilia Position Faculty -> Associate Professor Location Università Di Bologna Phone Phone: 0512093038 Mail This e-mail address is being protected from spam bots, you need JavaScript enabled to view it     Publications M. Omana, D. Giaffreda, C. Metra, TM Mak, S.Tam A, Rahman, "On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter", 2010 We present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despite the possible presence of significant process parameter variations 612 C. Metra, D. Rossi, TM. Mak, "Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?", 2007 to appear o IEEE Trans. on Computers J. M. Cazeaux, D. Rossi, C. Metra, F. Lombardi, "A Novel Dual-Walled CNT Bus Architecture with Reduced Cross-Coupling Features", 2006 in Proceedings of IEEE Conference on Nanotechnology, Cincinnati (Ohio, USA), July 16-20, 2006 D. Rossi, C. Steiner, C. Metra, "Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN", 2006 in Proc. of IEEE Design, Automation and Test in Europe (DATE 2006), Munich (Germany), March 6-10, 2006, pp. 59-64 C. Metra, D. Rossi, M. Omaña, J.M. Cazeaux, T.M. Mak, "Can Clock Faults Be Detected Through Functional Test?", 2006 Proceedings of 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'06), Prague (Czech Republic), April 18 - 21, 2006, pp. 168-173 D. Rossi, M. Omaña, C. Metra, A. Pagni, "Checker No-Harm Alarm Robustness", 2006 IEEE CS Proceedings 12th IEEE International On-Line Testing Symposium, Como (Italy), July 10-12, 2006, pp. 275-280 M. Omaña, J. M. Cazeaux, D. Rossi, C. Metra, "Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects", 2006 in Proc. of IEEE Design, Automation and Test in Europe (DATE 2006), Munich (Germany) March 6 - 10, 2006, pp. 170-175 C. Metra, M. Omaña, D. Rossi, J. M. Cazeaux, T.M. Mak, "Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation ", 2006 IEEE CS Proceedings 12th IEEE International On-Line Testing Symposium, Como (Italy), July 10-12, 2006, pp. 17-22 X. Ma, J. Huang, C. Metra, F. Lombardi, "Testing Reversible 1D Arrays of Molecular QCA", 2006 to appear on IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Washington DC, October 4-6, 2006 A. K. Nieuwland, A. Katoch, D. Rossi, C. Metra, "Coding Techniques for Low Switching Noise in Fault Tolerant Busses", 2005 IEEE CS Proceedings 11th IEEE International On-Line Testing Symposium, July 6-8, 2005, pp. 183-189. D. Rossi, A. K. Nieuwland, A. Katoch, C. Metra, "Exploiting ECC Redundancy to Minimize Crosstalk Impact", 2005 IEEE Design &Test of Computers, January-February 2005, pp. 59-70 M. Omaña, D. Rossi, C. Metra, "Low Cost and High Speed Embedded Two-Rail Code Checker", 2005 IEEE Transactions on Computers, Vol. 54, Issue 2, February 2005, pp. 153-164 M. Omaña, D. Rossi, C. Metra, "Low Cost Scheme for On-Line Clock Skew Compensation", 2005 IEEE CS Proceedings of 23rd IEEE VLSI Test Symposium, Palm Springs (California), May 1-5, 2005, pp. 90-95 D. Rossi, M. Omaña, F. Toma, C. Metra, "Multiple Transient Faults in Logic: an Issue for Next Generation ICs?", 2005 IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterrey (California), October 3-5, 2005, pp. 352-360. D. Rossi, A. K. Nieuwland, A. Katoch, C. Metra, "New ECC for Crosstalk Impact Minimization", 2005 IEEE Design & Test of Computers, July-August 2005, pp. 340-348 J. M. Cazeaux, M. Omaña, C. Metra, "Novel On-Chip Circuit for Jitter Testing in High-speed PLLs", 2005 IEEE Transactions on Instrumentations and Measurements, Vol. 54, Issue 5, October 2005, pp. 1779-1788. M. Omaña, O. Losco, C. Metra, A. Pagni, "On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization", 2005 IEEE CS Proceedings 11th IEEE International On-Line Testing Symposium, July 6-8, 2005, pp. 163-168 J. M. Cazeaux, D. Rossi, M. Omaña, C. Metra, A. Chatterjee, "On Transistor Level Gate Sizing for Increased Robustness to Transient Faults", 2005 IEEE CS Proceedings 11th IEEE International On-Line Testing Symposium, July 6-8, 2005, pp. 23-28. Y. S. Dhillon, A. U. Diril, A. Chatterjee, C. Metra, "Output Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits", 2005 IEEE CS Proceedings 11th IEEE International On-Line Testing Symposium, July 6-8, 2005, pp. 35-40. J. M. Cazeaux, D. Rossi, C. Metra, "Self-Checking Voter for High Speed TMR Systems", 2005 The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No. 4, August 2005, pp. 377-389. C. Metra, M. Omaña, D. Rossi, J. M. Cazeaux, T.M. Mak, "The Other Side of the Timing Equation: a Result of Clock Faults", 2005 IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterrey (California), October 3-5, 2005, pp. 169-177. C. Metra, T.M. Mak, M. Omaña, "Are Our Design For Testability Features Fault Secure?", 2004 IEEE CS Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), February 16-20, 2004, pp. 714-715 M. Omaña, D. Rossi, C. Metra, "Fast and Low Cost Deskew Buffer", 2004 IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes (France), October 11-13, 2004, pp. 202-210. C. Metra, T.M. Mak, M. Omaña, "Fault Secureness Need for Next Generation High Performance Microprocessor Design for Testability Structures", 2004 Proceedings of 2004 ACM International Conference on Computing Frontiers, Ischia (Italy), April 14-16, 2004, pp. 444-450. C. Metra, A. Ferrari, M. Omaña, A. Pagni, "Hardware Reconfiguration Scheme for High Availability Systems", 2004 IEEE CS Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 - 14, 2004, pp. 161-166. D. Rossi, A. Muccio, A. K. Neiuwland, A. Kotoch, C. Metra, "Impact of ECCs on Simultaneously Switching Outputs Noise for On-Chip Busses of High Reliability Systems", 2004 in IEEE CS Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 - 14, 2004, pp. 135-140. C. Metra, S. Di Francescantonio, T.M. Mak, "Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing", 2004 IEEE Transactions on Computers, Vol. 53, No. 5, May 2004, pp. 531-546 J. M. Cazeaux, M. Omaña, C. Metra, "Low-Area and Fast On-Chip Circuit for Jitter Measurement in Phase-Locked Loop", 2004 IEEE CS Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 - 14, 2004, pp. 17-22. M. Omaña, D. Rossi, C. Metra, "Model for Transient Fault Susceptibility of Combinational Circuits", 2004 The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 20, No. 5, October 2004, pp. 495-503. J. M. Cazeaux, D. Rossi, C. Metra, "New High Speed CMOS Self-Checking Voter", 2004 IEEE CS Proceedings 10th IEEE International On-Line Testing Symposium, Madeira (Portugal), July 12 - 14, 2004, pp. 58-63. C. Metra, M. Omaña, T.M. Mak, "Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing", 2004 in IEEE Proceedings of International Test Conference (ITC), Charlotte (NC), October 26- October 28, 2004, pp. 1223-1231. C. Metra, T.M. Mak, M. Omaña, "Should We Make Our Design for Testability Schemes Fault Secure?", 2004 Proceedings of The IEEE European Test Symposium, Aiaccio (Corsica), May, 2004, pp. 67-72 M. Favalli, C. Metra, "TMR Voting in the Presence of Crosstalk Faults at the Voter Inputs", 2004 IEEE Transactions on Reliability, Vol. 53, No. 3, September 2004, pp. 342-348 M. Omaña, G. Papasso, D. Rossi, C. Metra, "A Model for Transient Fault Propagation in Combinatorial Logic", 2003 IEEE CS Proceedings 9th IEEE International On-Line Testing Symposium, Kos (Greece), July 7 - 9, 2003, pp. 111-115. C. Metra, S. Di Francescantonio, M. Omaña, "Automatic Modification of Sequential Circuits for Self-Checking Implementation", 2003 IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA), November 2003, pp. 417-424 C. Metra, T.M. Mak, D. Rossi, "Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors", 2003 November IEEE CS Proceedings of The International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (MA) 63-70 C. Metra, L. Schiano, M. Favalli, "Concurrent Detection of Power Supply Noise", 2003 IEEE Transactions on Reliability, Vol. 52, No. 4, December 2003, pp. 469-475 L. Di Silvio, D. Rossi, C. Metra, "Crosstalk effect minimization for encoded bus", 2003 IEEE CS Proceedings 9th IEEE International On-Line Testing Symposium, Kos (Greece), July 7 - 9, 2003, pp. 214-218. D. Rossi, S. Cavallotti, C. Metra, "Error Correcting Codes for Crosstalk Effect Minimization", 2003 IEEE CS Proceedings of The International Symposium on Defect and Fault Toelrance in VLSI Systems, Boston (MA), November 2003, pp. 257-264 D. Rossi, C. Metra, "Error correcting strategy for high speed and density reliable flash memories", 2003 The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 19, No. 5, October 2003, pp. 511-521 M. Omaña, D. Rossi, C. Metra, "High Speed and Highly Testable Parallel Two- Rail Code Checker", 2003 IEEE CS Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich (Germany), March 4-7, 2003, pp. 608-613. M. Omaña, D. Rossi, C. Metra, "Novel Transient Fault Hardened Static Latch", 2003 IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), September 30 - October 2, 2003, pp. 886-892 D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland, C. Metra, "Power Consumption of Fault Tolerant Codes: the Active Elements", 2003 IEEE CS Proceedings 9th IEEE International On-Line Testing Symposium, Kos (Greece), July 7 - 9, 2003, pp. 61-67. C. Metra, S. Di Francescantonio, M. Favalli, B. Riccò, "Scan Flip-Flops with On-Line Testing Ability with respect to input Delay and Crosstalk Faults", 2003 Microelectronics Journal, Vol. 34, n. 1, January, 2003, pp. 23-29 L. Schiano, C. Metra, D. Marino, "Self-Checking Design, Implementation and Measurement of a Controller for Track-Side Railway Systems", 2003 IEEE Transactions on Instrumentation and Measurement, Vol. 52, No. 6, December 2003, pp. 1722-1728 C. Metra, S. Di Francescantonio, T. M. Mak, "Clock Faults' Impact on Manufacturing Testing and Their Possible Detection Through On-line Testing", 2002 IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), October 8-10, 2002, pp. 100-109 D. Rossi, V.E.S. van Dijk, R.P. Kleihorst, A.H. Nieuwland, C. Metra, "Coding Scheme for Low Energy Consumption Fault-Tolerant Bus", 2002 IEEE CS Proceedings 8th IEEE International On-Line Testing Workshop, Isle of Bendor (France), July 8-10, 2002, pp. 8-12. L. Schiano, C. Metra, D. Marino, "Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems", 2002 IEEE CS Proceedings 8th IEEE International On-Line Testing Workshop, Isle of Bendor (France), July 8-10, 2002, pp. 243-247. D. Rossi, C. Metra, B. Riccò, "Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories", 2002 IEEE CS Proceedings IEEE International Workshop on Memory Technology, Design and Testing, Isle of Bendor (France), July 10-12, 2002, pp. 27--31. C. Metra, M. Favalli, S. Di Francescantonio, B. Riccò , "On-Chip Clock Faults' Detector ", 2002 The Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, n. 4, August, 2002, pp. 555-564 M. Favalli, C. Metra, "On-Line Testing Approach for Very Deep-Submicron ICs", 2002 IEEE Design & Test, vol. March-April, 2002, pp. 16-23 C. Metra, S. Di Francescantonio, G. Marrale, "On-Line Testing of Transient faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits", 2002 IEEE CS Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 6-8, 2002, Vancouver (Canada), pp. 207-215 M. Favalli, C. Metra, "Problems due to open faults in the interconnections of self-checking data-paths", 2002 IEEE CS Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), March 4-8, 2002, pp. 612-617 C. Metra, L. Schiano, M. Favalli, B. Riccò, "Self-Checking Scheme for the On-Line Testing of Power Supply Noise", 2002 IEEE CS Proceedings of Design, Automation and Test in Europe (DATE) Conference, Paris (France), March 4-8, 2002, pp. 832-836 M. Favalli, C. Metra, "Single output distributed two-rail checker with diagnosing capabilities for bus based self-checking architectures", 2002 Journal of Electronic Testing: Theory and Applications, Vol. 18, n. 3, June 2002, pp. 273-283 C. Metra, S. Di Francescantonio, T. M. Mak, B. Riccò, "Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects", 2001 IEEE CS Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 24-26, 2001, pp. 357-365 M. Alderighi, S. D'Angelo, C. Metra, G. Sechi, "Novel Fault-Tolerant Adder Design for FPGA - Based Systems ", 2001 IEEE CS Proceedings of 7th IEEE International n-Line Testing Workshop, Giardini Naxos-Taormina (Italy), July 9-11, 2001, pp. 54-58 C. Metra, A. Pagano, B. Riccò, "On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems", 2001 IEEE Proceedings of International Test Conference (ITC), Baltimore (MD), October 30 - November 1, 2001, pp. 939-947 M. Favalli, C. Metra, "Optimization of error detecting codes for the detection of crosstalk originated errors", 2001 IEEE CS Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich (Germany), March 13-16, 2001, pp. 290-296 M. Favalli, C. Metra, "Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures", 2001 IEEE CS Proceedings of 7th IEEE International On-Line Testing Workshop, Giardini Naxos-Taormina (Italy), July 9-11, 2001, pp. 100-105 C. Metra, B. Riccò, "Soluzioni Hardware per Sistemi Integrati Digitali ad Alta Sicurezza", 2001 in Alta Frequenza Rivista di Elettronica, Vol. 13, No 3, Maggio-Giugno 2001, Associazione Elettrotecnica ed Elettronica Italiana, Milano, 2001, pp. 4-10